Download A Designer’s Guide to Built-In Self-Test by Charles E. Stroud PDF

By Charles E. Stroud

A fresh technological develop is the artwork of designing circuits to check themselves, known as a integrated Self-Test (BIST). this concept used to be first proposed round 1980 and has grown to turn into probably the most very important checking out thoughts on the present time, in addition to for the longer term. This booklet is written from a designer's point of view and describes the most important BIST techniques which have been proposed and applied in view that 1980, in addition to their merits and obstacles. The BIST methods contain the integrated common sense Block Observer, pseudo-exhaustive BIST recommendations, round BIST, scan-based BIST, BIST for normal buildings, BIST for FPGAs and CPLDs, mixed-signal BIST, and the mixing of BIST with concurrent fault detection concepts for online trying out. specific awareness is paid to system-level use of BIST which will maximize some great benefits of BIST via diminished checking out time and price in addition to excessive diagnostic answer. the writer spent 15 years as a dressmaker at Bell Labs the place he designed over 20 creation VLSI units and three construction circuit forums. 16 of the VLSI units contained BIST of varied forms for normal buildings and basic sequential good judgment, together with the 1st BIST for Random entry stories (RAMs), the 1st thoroughly self-testing built-in circuit, and the 1st BIST for mixed-signal platforms at Bell Labs. He has spent the earlier 10 years in academia the place his learn and improvement maintains to target BIST, together with the 1st BIST for FPGAs and CPLDs besides persisted paintings within the region of BIST for basic sequential common sense and mixed-signal platforms. He holds 10 US patents (with five extra pending) for numerous forms of BIST methods. as a result, the writer brings a special combination of information and event to this useful consultant for designers, try engineers, product engineers, procedure diagnosticians, and managers.

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Sample text

As the expected responses are read from the ORA ROM, they are compared to the actual output response of the CUT for each test vector being applied by the TPG. Any mismatch detected by the comparator is latched to indicate a failure has occurred during the BIST sequence. A single counter, clocked by the same clock signal as the input clock to the CUT, can be used to read the data from both ROMs and can also function as the test controller. In this simple but detailed BIST design, the BIST Start signal is assumed to be active high.

However, a bigger concern is determining the number and location of possible bridging fault sites in the first place. The possible fault sites for gate-level and transistor-level fault models are apparent from the circuit design long before physical layout since we are only concerned with the individual gates and transistors. Bridging faults, on the other hand, deal with pairs of wires and more specifically pairs of wires that are adjacent in the physical layout. Therefore, the possible fault sites to be considered for fault simulation is a concern in bridging fault simulation due to the simulation time, as well as the accuracy of the fault coverage results.

If a mismatch is obtained for any test vector, the faulty circuit has produced an erroneous response compared to the fault-free circuit and the fault (or set of faults) is considered to be detected. As soon as a fault is detected, most fault simulators will stop simulating that fault (this is often referred to as fault dropping) and restart simulation at the beginning of the set of test vectors with the next fault in the list being emulated. If there are no mismatches in the output response for the complete set of test vectors, then the fault is undetected.

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