By Charles E. Stroud
A up to date technological develop is the artwork of designing circuits to check themselves, known as a integrated Self-Test (BIST). This thought used to be first proposed round 1980 and has grown to turn into one of many most crucial checking out innovations on the present time, in addition to for the long run. This publication is written from a designer's viewpoint and describes the main BIST techniques which were proposed and carried out due to the fact that 1980, besides their benefits and barriers. The BIST techniques contain the integrated common sense Block Observer, pseudo-exhaustive BIST ideas, round BIST, scan-based BIST, BIST for normal buildings, BIST for FPGAs and CPLDs, mixed-signal BIST, and the mixing of BIST with concurrent fault detection suggestions for online checking out. specific recognition is paid to system-level use of BIST with a view to maximize the advantages of BIST via lowered trying out time and price in addition to excessive diagnostic answer. the writer spent 15 years as a dressmaker at Bell Labs the place he designed over 20 creation VLSI units and three construction circuit forums. 16 of the VLSI units contained BIST of varied forms for normal buildings and basic sequential common sense, together with the first BIST for Random entry stories (RAMs), the 1st thoroughly self-testing built-in circuit, and the 1st BIST for mixed-signal structures at Bell Labs. He has spent the previous 10 years in academia the place his study and improvement keeps to target BIST, together with the first BIST for FPGAs and CPLDs in addition to persisted paintings within the sector of BIST for basic sequential common sense and mixed-signal structures. He holds 10 US patents (with five extra pending) for numerous sorts of BIST methods. for that reason, the writer brings a distinct mix of information and event to this useful consultant for designers, attempt engineers, product engineers, method diagnosticians, and bosses.
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Extra info for A Designer s Guide to Built-in Self-Test
Unless specifically stated otherwise, the single fault model will be assumed in the subsequent sections and chapters. 6 Equivalent Faults and Fault Collapsing Under the single fault model, the number of gate-level stuck-at faults associated with each gate is twice the total number of inputs and outputs of the gate since each input or output can be either stuck-at-0 or stuck-at-1. 3 it is evident that some of these faults behave identically and cannot be distinguished from each other as a result of their faulty behavior.
This facilitates targeting the highest probability bridging fault sites during test development for the most efficient manufacturing testing. Or, if we wish to reduce the number of faults to be simulated, we can remove those potential bridging faults from the list that have the lowest probability of occurrence. Another important aspect of the capacitance extraction is the ability to determine the weighted fault coverage of a given set of manufacturing tests. 1), the weighted bridging fault coverage, is given by : where D is the number of detected faults, T is the total number of faults, and is the capacitance extracted for the bridging fault site .
Chapter 2. Fault Models, Detection, and Simulation 19 Chapter 2. 2 Transistor-Level Stuck Fault Model Gate-level fault models can accurately reflect the behavior of transistor faults in NMOS circuits, but the advent of CMOS brought with it the need for transistor fault models. The transistor-level stuck fault model allows any transistor to be either stuckon (also referred to as stuck-short) or stuck-off (also referred to as stuck-open). 4 illustrates the emulation of the transistor-level stuck fault model in a 2input CMOS NOR gate.